Verilog for Beginners: Register File

Introduction
Register File is a memory space present within the CPU. It is used by the CPU to fetch and hold the data from the secondary memory devices. It is faster compared to other memory devices as it is present within the processor. In RISC cores the register file is larger in size compared to CISC. Register file can be a static random access memory. Within these SRAM there are bits of memory labeled according to a binary code which will specify whether it is active or inactive.

A Register File Read operation functions as follows:
- Any value provided on output selection port (4-bit input Sel_o1) is used to select the content of the corresponding register to provide as output on the 32-bit output port Op1 on the positive edge of clock when the read enable switch is high.
- Any value provided on output selection port (4-bit input Sel_o2) is used to select the content of the corresponding register to provide as output on the 32-bit output port Op2 on the positive edge of clock when the read enable switch is high.
Figure 1. Block Diagram of Register File Read operation

A Register File Write operation functions as follows:
- Any value provided on the input selection port (4-bit input Sel_i1) is used to select the corresponding register into which the value from the 32-bit input port 1 is written to on the positive edge of clock when the write enable switch is high.
Figure 2. Block Diagram of Register File Write operation

Verilog Module
Figure 3 presents the Verilog module of the Register File. This Register File can store sixteen 32-bit values. The Register File module consists of a 32-bit data input line, Ip1 and two 32-bit data output lines, Op1 and Op2. The module is clocked using the 1-bit input clock line clk. The module also has a 1-bit enable line, EN and a 1-bit active high reset line, rst.

The Register File module also has two 4-bit output selection ports Sel_o1 and Sel_o2, and one 4-bit input selection port Sel_i1.

The 1-bit RD line is used to signal a data read operation on the Register File and the 1-bit WR line is used to signal a data write operation on the Register File. Both the RD and WR lines are active high.

When the RD line is high and there are valid register numbers in the output selection ports Sel_o1 and Sel_o2 then the Register File outputs the values in the corresponding registers to the output ports Op1 and Op2.

When the WR line is high and there is a valid register number in the input selection port Sel_i1 then the Register File writes the value on the input port Ip1 to the corresponding register in the Register File.

Figure 3. Verilog module of the Register File

Verilog Code for Register File (regFile.v)


module regFile( Ip1,
                sel_i1, 
                Op1,
                sel_o1, 
                Op2,
                sel_o2, 
                RD,
                WR, 
                rst,
                EN, 
                clk
              );      
input  [31:0]  Ip1; 
input  [3:0]  sel_i1,
              sel_o1,
              sel_o2; 
input  RD,
       WR; 
input  EN,
       clk,
       rst; 
output [31:0]  Op1,
               Op2; 
reg  [31:0]  Op1,
             Op2;       
reg [31:0]  regFile [0:15]; 
integer i; 
wire  sen; 
assign sen = clk || rst; 
always @ (posedge sen) 
begin 
 if (EN == 1) 
 begin 
  if (rst == 1) //If at reset 
   begin 
   for (i = 0; i < 16; i = i + 1) begin
    regFile [i] = 32'h0; 
   end 
   Op1 = 32'hx; 
   end 
  else if (rst == 0) //If not at reset 
   begin 
   case ({RD,WR}) 
    2'b00:  begin 
     end 
    2'b01:  begin //If Write only 
     regFile [sel_i1] = Ip1; 
     end 
    2'b10:  begin //If Read only 
     Op1 = regFile [sel_o1]; 
     Op2 = regFile [sel_o2]; 
     end 
    2'b11:  begin //If both active 
     Op1 = regFile [sel_o1]; 
     Op2 = regFile [sel_o2]; 
     regFile [sel_i1] = Ip1; 
     end 
    default: begin //If undefined 
      end 
   endcase 
   end 
  else; 
 end 
 else; 
end 
endmodule

Figure 4. Verilog code for Register File

Verilog Test Bench for Register File (regFile_tb.v)


`timescale 1ns / 1ps
module regFile_tb;
 // Inputs
 reg [31:0] Ip1;
 reg [3:0] sel_i1;
 reg [3:0] sel_o1;
 reg [3:0] sel_o2;
 reg RD;
 reg WR;
 reg rst;
 reg EN;
 reg clk;
 // Outputs
 wire [31:0] Op1;
 wire [31:0] Op2;
 // Instantiate the Unit Under Test (UUT)
 regFile uut (
               .Ip1(Ip1), 
               .sel_i1(sel_i1), 
               .Op1(Op1), 
               .sel_o1(sel_o1), 
               .Op2(Op2), 
               .sel_o2(sel_o2), 
               .RD(RD), 
               .WR(WR), 
               .rst(rst), 
               .EN(EN), 
               .clk(clk)
              );
 initial begin
  // Initialize Inputs
  Ip1  = 32'b0;
  sel_i1  = 4'b0;
  sel_o1  = 4'b0;
  sel_o2  = 4'b0;
  RD  = 1'b0;
  WR  = 1'b0;
  rst  = 1'b1;
  EN  = 1'b0;
  clk  = 1'b0;
  // Wait 100 ns for global reset to finish
  #100;        
  // Add stimulus here
   rst  = 1'b0;
   EN  = 1'b1;
   #20;
   WR  = 1'b1;
   RD = 1'b0;
   Ip1  = 32'habcd_efab;
   sel_i1  = 4'h0;
   #20;
   Ip1  = 32'h0123_4567;
   sel_i1  = 4'h1;
   #20;
   WR  = 1'b0;
   RD     = 1'b1;
   sel_o1  = 4'h0;
   sel_o2  = 4'h1;
 end 
   always begin
  #10;
  clk = ~clk;
 end 
endmodule

Figure 5. Verilog Test-bench for Register File

Timing Diagram

Figure 6. Timing diagram of Register File

Register File

Introduction

Verilog Module

Verilog Code for Register File (regFile.v)

Verilog Test Bench for Register File (regFile_tb.v)

Timing Diagram