Barrel Shifter

  1. Introduction


    A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers and in such an implementation the output of one mux is connected to the input of the next mux in a way that depends on the shift distance. The block diagram of a logical left shifting barrel shifter is shown in Figure 1.

    Figure 1. Block Diagram of Logical Left Shift Barrel Shifter

  2. Verilog Module


    The Verilog module of logical left shift barrel shifter is shown in Figure 2. It has one 8-bit input port, Ip, and 3-bit port shift_mag for left shift magnitude. The module presents 8-bit shifted value from output port Op.

    Figure 2. Verilog module of Logical Left Shift Barrel Shifter


  3. Verilog Code for the 8-bit Logical Left Shift Barrel Shifter (barrelShifter.v)



    1. module barrelShifter( Ip,
    2. Op,
    3. shift_mag
    4. );
    5. input [7:0] Ip; //The 8-bit Input line
    6. output [7:0] Op; //The 8-bit Output line
    7. input [2:0] shift_mag; //The 3-bit shift magnitude selection Input
    8. wire [7:0] ST1,ST2; //Two 8-bit intermediate lines
    9. //the barrel shifter implemented as array of MUX shown in the figure
    10. mux_2to1 m0 (1'b0, Ip[0], ST1[0], shift_mag[0]);
    11. mux_2to1 m1 (Ip[0], Ip[1], ST1[1], shift_mag[0]);
    12. mux_2to1 m2 (Ip[1], Ip[2], ST1[2], shift_mag[0]);
    13. mux_2to1 m3 (Ip[2], Ip[3], ST1[3], shift_mag[0]);
    14. mux_2to1 m4 (Ip[3], Ip[4], ST1[4], shift_mag[0]);
    15. mux_2to1 m5 (Ip[4], Ip[5], ST1[5], shift_mag[0]);
    16. mux_2to1 m6 (Ip[5], Ip[6], ST1[6], shift_mag[0]);
    17. mux_2to1 m7 (Ip[6], Ip[7], ST1[7], shift_mag[0]);
    18. mux_2to1 m00 (1'b0 , ST1[0], ST2[0], shift_mag[1]);
    19. mux_2to1 m11 (1'b0 , ST1[1], ST2[1], shift_mag[1]);
    20. mux_2to1 m22 (ST1[0], ST1[2], ST2[2], shift_mag[1]);
    21. mux_2to1 m33 (ST1[1], ST1[3], ST2[3], shift_mag[1]);
    22. mux_2to1 m44 (ST1[2], ST1[4], ST2[4], shift_mag[1]);
    23. mux_2to1 m55 (ST1[3], ST1[5], ST2[5], shift_mag[1]);
    24. mux_2to1 m66 (ST1[4], ST1[6], ST2[6], shift_mag[1]);
    25. mux_2to1 m77 (ST1[5], ST1[7], ST2[7], shift_mag[1]);
    26. mux_2to1 m000 (1'b0 , ST2[0], Op[0], shift_mag[2]);
    27. mux_2to1 m111 (1'b0 , ST2[1], Op[1], shift_mag[2]);
    28. mux_2to1 m222 (1'b0 , ST2[2], Op[2], shift_mag[2]);
    29. mux_2to1 m333 (1'b0 , ST2[3], Op[3], shift_mag[2]);
    30. mux_2to1 m444 (ST2[0], ST2[4], Op[4], shift_mag[2]);
    31. mux_2to1 m555 (ST2[1], ST2[5], Op[5], shift_mag[2]);
    32. mux_2to1 m666 (ST2[2], ST2[6], Op[6], shift_mag[2]);
    33. mux_2to1 m777 (ST2[3], ST2[7], Op[7], shift_mag[2]);
    34. endmodule
    Figure 3. Verilog Code for Logical Left Shift Barrel Shifter

  4. Verilog Code of the Test Bench for 8-bit Logical Left Shift Barrel Shifter (barrelShifter_tb.v)



    1. `timescale 1ns / 1ps
    2. module barrelShifter_tb;
    3. // Inputs
    4. reg [7:0] Ip;
    5. reg [2:0] shift_mag;
    6. // Outputs
    7. wire [7:0] Op;
    8. // Instantiate the Unit Under Test (UUT)
    9. barrelShifter uut (
    10. .Ip(Ip),
    11. .Op(Op),
    12. .shift_mag(shift_mag)
    13. );
    14. initial begin
    15. // Initialize Inputs
    16. Ip = 8'd0;
    17. shift_mag = 3'd0;
    18. // Wait 100 ns for global reset to finish
    19. #100;
    20. // Add stimulus here
    21. Ip = 8'd16;
    22. shift_mag = 3'd2;
    23. #20;
    24. Ip = 8'd4;
    25. shift_mag = 3'd2;
    26. end
    27. endmodule
    Figure 4. Verilog Test-bench for Logical Left Shift Barrel Shifter

  5. Timing Diagram


    Figure 5. Timing diagram of Logical Left Shift Barrel Shifter