8-to-1 Multiplexer

1. Introduction

   
   An 8-to-1 multiplexer is a digital device that selects one of the eight inputs lines to the output line by using three-bit selection line. The block diagram of 8-to-1 Mux is shown in Figure 1. A 2ⁿ-to-1 multiplexer needs n bit selection line to select one of the 2ⁿ inputs to the output.
   
   

   

   Figure 1. Block diagram of 8-to-1 multiplexer




2. Truth Table

   
   Figure 2 shows the truth table of the 8-to-1 multiplexer. I1 to I8 are the input lines, S1 - S3 are the selection lines and O is the output line.
   
   

   

   Figure 2. Truth table of  8-to-1 multiplexer




3. Verilog Module

   Figure 3 shows the Verilog module of the 8-to-1 multiplexer. The 8-bit ports In1 to In8 are input lines of the multiplexer. The Sel port is the 3-bit selection line which is required to select between the eight input lines. 8-bit port Out is the output line of the multiplexer.
   
   

   

   Figure 3. Verilog module of 8-to-1 multiplexer




4. Verilog Code for the 8-to-1 Multiplexer (mux8to1.v)

   
   

   
   

   
   module mux8to1( Out,
     Sel,
     In1,
     In2,
     In3,
     In4,
     In5,
     In6,
     In7,
     In8
     ); 
   
   input [7:0]  In1,
     In2,
     In3,
     In4,
     In5,
     In6,
     In7,
     In8; //The eight 8-bit input lines of the Mux 
   input [2:0] Sel; //The three bit selection line 
   
   output [7:0] Out; //The single 8-bit output line of the Mux 
   
   reg [7:0] Out; 
   
   //Check the state of the input lines 
   always @ (In1 or In2 or In3 or In4 or In5 or In6 or In7 or In8 or Sel) 
   begin 
    case (Sel) 
     3'b000 : Out = In1; 
     3'b001 : Out = In2; 
     3'b010 : Out = In3; 
     3'b011 : Out = In4; 
     3'b100 : Out = In5; 
     3'b101 : Out = In6; 
     3'b110 : Out = In7; 
     3'b111 : Out = In8; 
     default : Out = 8'bx; 
     //If input is undefined then output is undefined 
    endcase 
   end  
   endmodule
   
   

   Figure 4. Verilog Code for 8-to-1 multiplexer




5. Verilog Test Bench for 8-to-1 Multiplexer (mux8to1_tb.v)

   
   

   
   

   
   `timescale 1ns / 1ps
   
   module mux8to1_tb;
   
    // Inputs
    reg [2:0] Sel;
    reg [7:0] In1;
    reg [7:0] In2;
    reg [7:0] In3;
    reg [7:0] In4;
    reg [7:0] In5;
    reg [7:0] In6;
    reg [7:0] In7;
    reg [7:0] In8;
   
    // Outputs
    wire [7:0] Out;
    
    //temporary variable
    reg [2:0] count = 3'd0;
    
    // Instantiate the Unit Under Test (UUT)
    mux8to1 uut (
     .Out(Out), 
     .Sel(Sel), 
     .In1(In1), 
     .In2(In2), 
     .In3(In3), 
     .In4(In4), 
     .In5(In5), 
     .In6(In6), 
     .In7(In7), 
     .In8(In8)
    );
   
    initial begin
     // Initialize Inputs
     Sel = 0;
     In1 = 0;
     In2 = 0;
     In3 = 0;
     In4 = 0;
     In5 = 0;
     In6 = 0;
     In7 = 0;
     In8 = 0;
   
     // Wait 100 ns for global reset to finish
     #100;
           
     // Add stimulus here
     Sel = 3'd0;
     In1 = 8'd0;
     In2 = 8'd1;
     In3 = 8'd2;
     In4 = 8'd3;
     In5 = 8'd4;
     In6 = 8'd5;
     In7 = 8'd6;
     In8 = 8'd7;
     //Selection input generation
     for (count = 0; count < 8; count = count + 1'b1)
     begin
      Sel = count;
      #20;
     end
    end      
   endmodule
   
   

   Figure 5. Verilog Test-Bench for 8-to-1 multiplexer




6. Timing Diagram

   

   Figure 6. Timing diagram of 8-to-1 multiplexer