3-to-8 Decoder

1. Introduction

   
   A n to 2ⁿ decoder is a combinatorial logic device which has n input lines and 2ⁿ output lines. For each possible combination of n input binary lines, one and only one output signal will be logic 1. Thus, the decoder is a min-term generator in which each output corresponds to one min-term. Decoders are important logic blocks that find a wide variety of applications in the design of digital systems.
   

   Input: (log₂n)
   Output: n bits (exactly one output pins is 1, rest of the pins are 0)

   Example: 3-8 decoder
   

   Input: 3 bits representing a binary input number
   Output: 1 bit corresponding to the value of the binary input number is set to 1

   Figure 1 shows the block diagram of the 3-to-8 decoder.
   
   

   

   Figure 1. Block diagram of a 3-to-8 decoder

   
   

2. Truth Table

   
   Figure 2 shows the truth table of a 3-to-8 decoder. Ip0 to Ip2 are the binary input lines and the Op0 to Op7 are the eight output lines.
   
   

   

   Figure 2. Truth table of 3-to-8 decoder.

   
   

3. Verilog Module

   
   Figure 3 presents the Verilog module of the 3-to-8 decoder. The module takes three 1-bit binary values from the three input ports Ip0 to Ip2. The eight 1-bit binary value outputs are presented in eight output ports Op0 to Op7. The decoder function is controlled by using an enable signal, EN.
   
   

   

   Figure 3. Verilog module of 3-to-8 decoder.

   
   

4. Verilog Code for 3-to-8 Decoder (decoder3to8.v)

   
   

   
   

   
   module decoder3to8( Ip0,
      Ip1,
      Ip2,
      Op0,
      Op1,
      Op2,
      Op3,
      Op4,
      Op5,
      Op6,
      Op7,
      EN
      ); 
   
   input  Ip0,
    Ip1,
    Ip2; //The three Input lines of the decoder 
   input EN; //The decoder Enable input. High active. 
   output reg Op0=0,
     Op1=0,
     Op2=0,
     Op3=0,
     Op4=0,
     Op5=0,
     Op6=0,
     Op7=0; 
      
   always @ (EN,Ip2,Ip1,Ip0) 
   begin 
    Op0=0;
    Op1=0;
    Op2=0;
    Op3=0;
    Op4=0;
    Op5=0;
    Op6=0;
    Op7=0; 
    if (EN==1'b1) 
    begin 
    case ({Ip2,Ip1,Ip0}) 
    3'b000: Op0=1; 
    3'b001: Op1=1; 
    3'b010: Op2=1; 
    3'b011: Op3=1; 
    3'b100: Op4=1; 
    3'b101: Op5=1; 
    3'b110: Op6=1; 
    3'b111: Op7=1; 
    default: begin 
     Op0=0;
     Op1=0;
     Op2=0;
     Op3=0;
     Op4=0;
     Op5=0;
     Op6=0;
     Op7=0; 
     end 
     endcase 
    end 
   end
   endmodule
   
   

   Figure 4. Verilog Code for 3-to-8 decoder

   
   

5. Verilog Test Bench for 3-to-8 Decoder (decoder3to8_tb.v)

   
   

   
   

   
   `timescale 1ns / 1ps
   
   module decoder3to8_tb;
   
    // Inputs
    reg Ip0;
    reg Ip1;
    reg Ip2;
    reg EN;
   
    // Outputs
    wire Op0;
    wire Op1;
    wire Op2;
    wire Op3;
    wire Op4;
    wire Op5;
    wire Op6;
    wire Op7;
   
    //temporary variable
    reg [2:0] count = 3'd0;
    
    // Instantiate the Unit Under Test (UUT)
    decoder3to8 uut (
     .Ip0(Ip0), 
     .Ip1(Ip1), 
     .Ip2(Ip2), 
     .Op0(Op0), 
     .Op1(Op1), 
     .Op2(Op2), 
     .Op3(Op3), 
     .Op4(Op4), 
     .Op5(Op5), 
     .Op6(Op6), 
     .Op7(Op7), 
     .EN(EN)
    );
   
    initial begin
     // Initialize Inputs
     Ip0 = 1'b0;
     Ip1 = 1'b0;
     Ip2 = 1'b0;
     EN = 1'b0;
   
     // Wait 100 ns for global reset to finish
     #100;
         
     // Add stimulus here
     EN = 1'b1;
     #20;
     for (count = 0; count < 8; count = count + 1'b1)
     begin
      {Ip0,Ip1,Ip2} = {Ip0,Ip1,Ip2} + 1'b1;
      #20;
     end
     EN = 1'b0;
    end      
   endmodule
   
   

   Figure 5. Verilog Test-bench for 3-to-8 decoder

   
   

6. Timing Diagram

   
   

   

   Figure 6. Timing diagram of 3-to-8 decoder