D Flip-Flop

  1. Introduction

    The output of a D Flip-Flop tracks the input, making transitions which match those of the input. The D in D Flip-Flop stands for Data i.e. this Flip-Flop stores the value on the data line. It can be thought of as a basic memory cell. A D Flip-Flop can be made from a Set/Reset Flip-Flop by tying the set line to the reset line through an inverter. The output of the Flip-Flop may be clocked. If the output is clocked then the D Flip-Flop is synchronous D Flip-Flop. Synchronous D Flip-Flop, thus, has output which is synchronized with the either the rising edge or the falling edge of the input clock pulse. The block diagram of synchronous D Flip-Flop is shown in Figure 1.

    Figure 1. Block diagram of synchronous D Flip-Flop

  2. Truth Table

    Figure 2 shows the truth table of synchronous D Flip-Flop which is clocked to the rising edge of input clock. The inputs to the D Flip-Flop are data-bit D, and control lines reset and clock. There are two outputs Q and Q'.

    Figure 2. Truth table of synchronous D Flip-Flop

  3. Verilog Module

    Figure 3 shows the Verilog module of D Flip-Flop. The input to the module is a 1-bit input data line D. The control lines to the module include a 1-bit clock line Clk which is supplied by the 50 MHz on-board clock generator and a 1-bit active high reset. The output lines are Q and Qbar (complement of output line Q). The output line Q takes the same value as that in the input line D on the rising edge of the clock line Clk when the reset line is at low.

    Figure 3. Verilog module of synchronous D Flip-Flop

  4. Verilog Code for synchronous D Flop-Flop (DFF.v)


      

    1. module DFF( Q,
      2. 

    2.   Qbar,
      3. 

    3.   D,
      4. 

    4.   Clk,
      5. 

    5.   Reset
      6. 

    6.     );
      7. 

    7. output  reg  Q; 
      8. 

    8. output   Qbar; 
      9. 

    9. input   D, 
      10. 

    10.   Clk, 
      11. 

    11.   Reset; 
      12. 

    12. assign Qbar = ~Q; 
      13. 

    13. always @(posedge Clk) 
      14. 

    14. begin 
      15. 

    15.  if (Reset == 1'b1) //If not at reset 
      16. 

    16.   Q = 1'b0;
      17. 

    17.  else 
      18. 

    18.   Q = D;
      19. 

    19. end 
      20. 

    20. endmodule
      21.
    Figure 4. Verilog code for synchronous D Flip-Flop

  5. Verilog Test Bench for synchronous D Flop-Flop (DFF_tb.v)


      

    1. `timescale 1ns / 1ps
      2. 

    2. module DFF_tb;
      3. 

    3.  // Inputs
      4. 

    4.  reg D;
      5. 

    5.  reg Clk;
      6. 

    6.  reg Reset;
      7. 

    7.  // Outputs
      8. 

    8.  wire Q;
      9. 

    9.  wire Qbar;
      10. 

    10.  // Instantiate the Unit Under Test (UUT)
      11. 

    11.  DFF uut (
      12. 

    12.   .Q(Q), 
      13. 

    13.   .Qbar(Qbar), 
      14. 

    14.   .D(D), 
      15. 

    15.   .Clk(Clk), 
      16. 

    16.   .Reset(Reset)
      17. 

    17.   );
      18. 

    18.  initial begin
      19. 

    19.   // Initialize Inputs
      20. 

    20.   D  = 1'b0;
      21. 

    21.   Clk  = 1'b0;
      22. 

    22.   Reset   = 1'b1;
      23. 

    23.   // Wait 100 ns for global reset to finish
      24. 

    24.   #100;
      25. 

    25.   // Add stimulus here
      26. 

    26.   Reset = 1'b0;
      27. 

    27.   #20;
      28. 

    28.   forever #40 D = ~ D;
      29. 

    29.  end
      30. 

    30.    always #10 Clk = ~Clk;  
      31. 

    31. endmodule
      32.
    Figure 5. Verilog Test bench for synchronous D Flip-Flop.

  6. Timing Diagram


    Figure 6. Timing diagram of synchronous D Flip-Flop

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