4-bit Carry Ripple Adder

1. Introduction

   
   A N-bit full adder can be designed by cascading N number of 1-bit full adders. Each full adder takes a carry-in C_in, which is the carry-out C_out of the previous adder. This kind of chain of adders forms a ripple-carry adder, since each carry-bit "ripples" to the next full adder. The layout of a ripple-carry adder is simple, which allows for fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry-bit to be calculated from the previous full adder. A 4-bit ripple carry adder formed by cascading four 1-bit full adders is shown in Figure 1.
   
   

   

   Figure 1. 4-bit Carry Ripple Adder formed by cascading four full adders




2. Verilog Module

   
   Figure 2 shows the Verilog module of a 4-bit carry ripple adder. A and B are the two 4-bit input ports which is used to read in the two 4-bit numbers that are to be summed up. The 1-bit carry-in input port C_in is used to read in a carry bit, if another instance of the ripple carry adder is cascaded towards lesser significant stage. The 4-bit sum generated by the adder is presented in the 4-bit output port Sum and 1-bit carry-out in the C_out output port. The carry out, C_out provides a carry-bit, if another instance of the ripple carry adder is cascaded towards more significant stage.
   
   

   

   Figure 2. Verilog module of a 4-bit Ripple Carry Adder




3. Verilog Code for 4-bit Carry Ripple Adder (Adder4bit.v)

   
   

   
   

   
   `timescale 1ns / 1ps
   module Adder4bit(A,
                    B,
                    Cin,
                    Sum,
                    Cout
                   );
   input  [3:0]  A,
                 B;
   input         Cin;
   output  [3:0] Sum;
   output        Cout;
   wire [2:0] transferC;
   fullAdder FA1 ( .In1(A[0]),
                   .In2(B[0]),
                   .Cin(Cin),
                   .Sum(Sum[0]),
                   .Cout(transferC[0])
                  );
   fullAdder FA2 ( .In1(A[1]),
                   .In2(B[1]),
                   .Cin(transferC[0]),
                   .Sum(Sum[1]),
                   .Cout(transferC[1])
                   );
   fullAdder FA3 ( .In1(A[2]),
                   .In2(B[2]),
                   .Cin(transferC[1]),
                   .Sum(Sum[2]),
                   .Cout(transferC[2])
                  );
   fullAdder FA4 ( .In1(A[3]),
                   .In2(B[3]),
                   .Cin(transferC[2]),
                   .Sum(Sum[3]),
                   .Cout(Cout)
                  );
   endmodule
   
   

   Figure 3. Verilog Code for 4-bit Ripple Carry Adder




4. Verilog Test Bench for 4-bit Ripple Carry Adder (Adder4bit_tb.v)

   
   

   
   

   
   `timescale 1ns / 1ps
   module Adder4bit_tb;
    // Inputs
    reg [3:0] A;
    reg [3:0] B;
    reg Cin;
    // Outputs
    wire [3:0] Sum;
    wire Cout;
    // Instantiate the Unit Under Test (UUT)
    Adder4bit uut (
                    .A(A), 
                    .B(B), 
                    .Cin(Cin), 
                    .Sum(Sum), 
                    .Cout(Cout)
                   );
    initial begin
     // Initialize Inputs
     A    = 4'b0;
     B    = 4'b0;
     Cin  = 4'b0;
     // Wait 100 ns for global reset to finish
     #100;
     // Add stimulus here
     A    = 4'b1011;
     B    = 4'b0100;
     Cin  = 4'b0;
     #20;
     A    = 4'd1111;
     B    = 4'd1101;
     Cin  = 4'b1;
    end
   endmodule
   
   

   Figure 4. Verilog Test-bench for 4-bit Ripple Carry Adder




5. Timing Diagram

   
   

   

   Figure 5. Timing Diagram of 4-bit Carry Ripple Adder